1. Technical Field
The disclosure relates to a method for measuring a via bottom profile.
2. Background
Conventionally, a chip is fabricated in a two-dimensional (2D) space, though as complexity of the chip increases, horizontal area thereof in the 2D space is increased, so that the Moore's Law cannot be continually effective. Therefore, different chips are considered to be stacked for integration, so that three-dimensional (3D) chips are generated. By using a through-silicon via (TSV) package technique, the vertically stacked chips are electrically connected, so that a fabrication quality of the TSV and a measurement accuracy thereof may obviously influence a yield of the chip. However, the TSV generally has a high aspect ratio, and a depth and a via bottom profile thereof cannot be directly measured through an optical microscope.
Therefore, it was suggested by utilizing a chromatic confocal sensor which operates in the near infrared (NIR) region of the spectrum to measure a depth of a via in a wafer, as disclosed by U.S. Pat. No. 7,738,113 B1. In this patent, the chromatic confocal sensor is used to measure from a bottom of the wafer, where a thickness of the wafer is first measured, i.e. a distance between the bottom and the top of the wafer, and then a distance between a bottom of the via and the bottom of the wafer is measured. Then, the depth of the via is obtained by subtracting the two distances.
However, a method for measuring a via bottom profile of the TSV is still not disclosed.